1. Field of the Invention
The present invention relates to semiconductor memory elements and more particularly to dynamic random access memory cells having stacked capacitors of fin structures and a method of making thereof.
2. Description of the Prior Art
Presently, semiconductor memory elements have a tendency to be highly integrated on a semiconductor chip. This high integration is achieved by increasing the density of the semiconductor memory elements on the chip. However, this increase in density results in a decrease in the area of the cell regions of the semiconductor memory elements. For obtaining a sufficient capacitance in a small cell region, there have been various developments such as dielectric materials having high dielectric constants and superior characteristics, methods of increasing the capacitor region, and methods for reducing the thickness of the dielectric layers.
The currently developed structures of capacitors capable of increasing the capacitor region are, for example, a stack structure, a trench structure, a stack-trench structure, a fin structure and a cylinder structure. Although these structures can increase the capacitor region, they require complex additional processing. As a result, they have been used sparingly in increasing the capacitor region of dynamic memory cells.
An example of one of the methods of increasing the capacitor region will now be described in conjunction with the manufacture of a DRAM cell having capacitors of what are known as fin structures.
FIGS. 1a to 1g are schematic sectional views illustrating a method of making a DRAM cell having stacked capacitors of fin structures. As shown in FIG. 1a, field oxide layer 2 is first grown on silicon substrate 1 so that silicon substrate 1 is divided into active regions and field regions. Subsequently, gate oxide layer 3a, polysilicon layer 3 and cap gate oxide layer 3b are formed in turn on the active and field regions. Cap gate oxide layer 3b, polysilicon layer 3 and gate oxide layer 3a are subjected to a photoetching process so as to form polysilicon gate structures (word lines) as shown in FIG. 1a. Silicon substrate 1 is then subjected to a impurity ion injection to form source and drain regions 4, also as shown in FIG. 1a.
As shown in FIG. 1b, Si.sub.3 N.sub.4 layer 5 (Si.sub.3 N.sub.4 is known as "nitride") is deposited over the surface of silicon substrate 1. As discussed below, Si.sub.3 N.sub.4 layer 5 is used as an etch stop layer in a subsequent processing step.
As shown in FIG. 1c, SiO.sub.2 layer 6, polysilicon layer 7 for a first fin of the storage node and SiO.sub.2 layer 8 are deposited in turn on Si.sub.3 N.sub.4 layer 5. Thereafter, an opening for a storage node buried contact is formed by a dry etching process.
As shown in FIG. 1d, polysilicon layer 9 is deposited on the overall exposed surface. Polysilicon layer 9 is formed as to contact the remaining portions of polysilicon layer 7 and also region 4 to form a buried contact as shown in FIG. 1d.
As shown in FIG. 1e, storage nodes are then defined by using a mask having a predetermined pattern. That is, polysilicon layers 7 and 9 (for the storage node) and SiO.sub.2 layers 6 and 8 are etched by a dry etching process with Si.sub.3 N.sub.4 layer 5 serving as an etch stop layer.
As shown in FIG. 1f, remaining SiO.sub.2 layers 6 and 8 between polysilicon layers 7 and 9 for the storage node and Si.sub.3 N.sub.4 layer 5 are completely removed by a wet etching process. Subsequently, dielectric layer 10 (denoted by a thick line in FIG. 1g) is formed on the overall exposed surface of the storage node defined by the remaining portions of polysilicon layers 7 and 9 (denoted 9, 7 in FIG. 1g).
As shown in FIG. 1g, polysilicon layer 11 for a plate node is deposited over the overall exposed surface. Polysilicon layer 11 subsequently is defined by mask and etching processes, and SiO.sub.2 layer 12 for insulating is deposited on the overall exposed surface. SiO.sub.2 layer 12 and Si.sub.3 N.sub.4 layer 5 are then etched by a dry etching process so as to form bit line contact holes. Thereafter, metal is deposited on the overall exposed surface, and the deposited metal layer is subsequently defined by mask and dry etching processes to form bit line 14. Thus, a DRAM cell having stacked capacitors of fin structures is obtained.
However, such prior art DRAM cells having stacked capacitors of fin structures have the following problems.
First, the process used to produce these structures is complicated due to repeated mask processing steps.
Second, silicon surface 1 at the buried contact regions may be easily damaged because the buried contact regions are formed by a dry etching process. As a result, the junction quality at the buried contact can be deteriorated, and the refresh time for the memory cell increased.
Third, the corner edge angles at the etched portions by the dry etch process are approximately 90.degree., which can cause irregularities in the thickness of the dielectric layer deposited on and around the etched portions. As a result, the deposited dielectric layer may be easily damaged, thereby resulting in the leakage of current.